The complexity of modern electronics, particularly data processors, has increased the likelihood of a manufacturing defect occurring in an integrated circuit (IC) chip. To increase the reliability of integrated circuits and to detect faulty ICs more rapidly, chip manufacturers commonly to incorporate built-in self-test (BIST) circuitry in many types of complex IC chips. BIST circuits are commonly used for memories, such as static random access memories (SRAM), dynamic random access memories (DRAM), flash RAM, and the like, and particularly cache memories. State-of-the-art chip level BIST circuitry uses a dedicated hardware controller to execute the BIST testing and to report the pass or fail result to an external device. BIST tests may be automatically generated for a given block of logic.
A BIST circuit for a cache memory typically performs some type of repetitive testing on the tag array of the cache memory. For example, a conventional BIST circuit may test one location in a tag array by “marching” Logic 1 values, Logic 0 values, and checkerboard patterns into the entry. In this type of testing, for example, Logic 1 values are shifted (i.e., “marched”) into the tag array one bit position at a time until the entire location is filled with Logic 1 values. The contents of the tag array location are tested and verified after each Logic 1 is shifted in. This procedure is repeated for Logic 0 values and for a checkerboard pattern (i.e., alternating Logic 1 and Logic 0 values). After these tests are complete, the entire test cycle is repeated for each of the remaining tag array locations.
However, while the above-described testing procedure thoroughly tests the tag array logic, conventional BIST circuits for testing cache memories fail to adequately test the remaining portions of the cache memory. Most notably, the comparator logic that determines cache hits and cache misses is not tested by conventional BIST circuitry.
Therefore, there is a need in the art for improved BIST circuitry for testing the cache memories of data processors and other large-scale integrated circuit (IC) chips. In particular, there is a need for BIST circuitry that adequately tests the comparator logic circuitry of a cache memory.